1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2011-077085, filed Mar. 31, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
As a semiconductor device disclosed in Japanese Patent Application Publication No. JPA 2001-210801, a DRAM (dynamic random-access memory) has an MOS (metal oxide semiconductor) transistor that has a trench formed in a semiconductor substrate, a gate insulating film formed in the trench, a gate electrode (buried gate electrode) provided in the trench, an insulating film (for example, a silicon oxide film) that buries a depression (part of the above-noted trench) formed in the top of the gate electrode so as to reach the surface of the semiconductor substrate, a first impurity diffusion region (drain region) formed in the semiconductor substrate positioned at one side of the trench, and a second impurity diffusion region (source region) formed in the semiconductor substrate positioned at the other side of the trench.
In the case of a DRAM constituted as noted above, the constitution is such that, the bottom surface of the source/drain diffusion layer formed in the surface of the semiconductor substrate, that is, the junction is in contact with the gate insulating film at a side wall part of the trench.
Therefore, if the interface state at the interface between the gate insulating film and the semiconductor substrate (silicon substrate) is high (or, stated differently, if there are many defects due to dangling bonds of single-crystal silicon at the surface of the semiconductor substrate making contact with the gate insulating film) there is a problem of a leakage current occurring via a defect in a part making contact with the above-noted source/drain diffusion layer junction.
In particular, in a DRAM, the electrical charge stored in a capacitive element connected to the drain diffusion layer leaks as a leakage current. These phenomena can give influences to the refresh characteristics.
In Japanese Patent Application Publication No. JPA 11 (2000)-317500, the hydrogen annealing after the formation of multi-level interconnects can be carried out for reducing the above-noted junction leakage current.